p1: Counter Ready
PC: 0 · SP: 255 · Cycles: 0 · Z=0 N=0 O=0
R0: 0R1: 0R2: 0R3: 0R4: 0R5: 0R6: 0R7: 0
Data stack: Empty · Call frames: Empty
Private memory: 0 / 256 nonzero bytes
All bytes are zero.
No output yet.
From one instruction to several tasks
Systems lab
Give programs turns on a CPU. Watch each private machine pause, sleep, wait, and resume.
This is an educational model, not a full operating system or hardware emulator. Each process has its own eight registers and 256-byte memory. Cores execute one instruction per simulated tick; round-robin scheduling gives a ready process a bounded turn.
Programs and input stay in this browser. No accounts, network services, or student records are needed.
Core 0
Idle
Instructions in this turn: 0Ready queue: p1 · Interrupt queue: Empty
Add a process
Counter, Fibonacci, and calculator run locally in the same tested emoji CPU. Edit them or add your own program. This lab has no filesystem or network emulator.
Wake a waiting process
INPUT with an empty queue waits at the same PC without consuming a CPU cycle. Deliver an integer and then use Step or Run. SLEEP releases a normal process until its simulated wake time.
Process control blocks
A process control block (PCB) records the machine state needed to continue a program. Open a memory summary to inspect nonzero bytes. Memory belongs to that process; the stack and call frames are separate from the memory grid.
Scheduler timeline
The latest 80 events show actual process and core assignments, executed source instructions, output, and context changes. The complete timeline remains in this local simulation until Reset.
- 0 ms · Process added
p1Event details
Counter joined the ready queue.