Scheduling, Cores and Events · Lesson 25 of 30 · about 15 minutes
Cooperative Scheduling
Take turns between tasks and distinguish policy from CPU instructions.
01 / Explain
Understand the idea
One CPU executes one instruction at a time. A scheduler chooses which task runs next. Cooperative tasks yield control voluntarily; preemptive scheduling gives each task a bounded instruction quantum. The systems lab shows round-robin scheduling with an adjustable quantum and explicit task events.
Our VM challenge is a small cooperative dispatcher: task A advances its own counter, then task B advances its own counter. CALL/RETURN express the turn-taking. SLEEP records a requested delay; synchronous CPU checks do not wait, while the timed lab honors it.
02 / Try
Watch it happen
The output order is 1 then 101. Run at a visible speed to observe the delay; use the systems lab to compare instruction quantum sizes.
LOAD 1
CALL taskA
CALL taskB
HALT
taskA: PRINT
SLEEP 500
RETURN
taskB: LOAD 101
PRINT
RETURNUse Step to follow one instruction at a time. You can change the example and replay it.
03 / Challenge
Make it work
Read a number of rounds from 0 through 3. Start task A’s counter at 0 and task B’s at 100. Each round, call A to increment and print its counter, then B to increment and print its counter.
The checker runs your current editor program in a fresh machine for each of 3 test cases. It supplies inputs and seeded memory itself; the lab’s current output and memory do not decide your result.
INPUT
COPY R0 R3
LOAD 0 R1
LOAD 100 R2
LOOP R3
CALL taskA
CALL taskB
RETURN
HALT
taskA:
# Advance R1, print, return.
RETURN
taskB:
# Advance R2, print, return.
RETURNNeed a hint?
Each task owns a different register, and each must RETURN to the dispatcher.
Reveal a worked solution
Read the program, predict each instruction’s effect, then step through it in the lab.
INPUT
COPY R0 R3
LOAD 0 R1
LOAD 100 R2
LOOP R3
CALL taskA
CALL taskB
RETURN
HALT
taskA: LOAD R1
ADD 1
COPY R0 R1
PRINT
SLEEP 0
RETURN
taskB: LOAD R2
ADD 1
COPY R0 R2
PRINT
SLEEP 0
RETURNEmoji CPU lab
Emoji program
Type LOAD, ADD, or another opcode then Space to insert emoji. Ctrl/⌘ + Enter runs or pauses; Escape pauses; Ctrl/⌘ + ] indents. Tab moves focus. Labels use a colon. Jumps use zero-based instruction addresses.
Instruction map and breakpoints (0)
Breakpoints stop before an instruction. Run resumes past the stopped breakpoint once; Step executes it directly. Editing source clears old breakpoints and machine state.
CPU registers
- R0
- 0
- R1
- 0
- R2
- 0
- R3
- 0
- R4
- 0
- R5
- 0
- R6
- 0
- R7
- 0
Stacks and loop frames
SP = 255 − data depth − call depth. The stack is separate from memory.
Data stack (bottom → top)
Empty
Call return addresses (bottom → top)
Empty
Loop frames
Empty
Output and input
Run a PRINT instruction to see output.
Queued input: Empty
Memory · 256 bytes · 0 nonzero
Each cell shows address:value. R = read this step; W = written this step. Select a cell to inspect or initialize it before execution. Use arrow keys to move, Home/End for the row, and Ctrl/⌘ + Home/End for the whole memory.
Execution trace · 0 entries
Recent entries below. Inspect any zero-based index to see complete detached before/after state.
Check your challenge
You can run this check any time. Every case must pass to record completion.
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