Teacher answer key

Scheduling, Cores and Events

Gather four kinds of evidence: prediction of relevant state; behavior across varied cases including boundaries; explanation using trace/state evidence; and a reasoned correction of one mismatch. Mark each as emerging, with support or independent using paper or your school’s existing approved process. A challenge pass is machine-behavior evidence, not proof of authorship or complete mastery. Accept equivalent correct programs; the public key is a model, not the only possible answer.

Public teaching material. Solutions are examples; equivalent correct programs may also pass the actual checks.

25. Cooperative Scheduling

Take turns between tasks and distinguish policy from CPU instructions.

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1. Predict and trace

Before running the Try program, predict its output and trace the first three executed instructions. Track the relevant registers, flags or memory as needed. Then step the program to compare.

LOAD 1
CALL taskA
CALL taskB
HALT
taskA: PRINT
SLEEP 500
RETURN
taskB: LOAD 101
PRINT
RETURN

Queue input: None

Initialize memory: All bytes initially zero

Try prediction key

Output: 1, 101

Instruction	PC before	PC after	R0 before	R0 after	Relevant state	Output
LOAD	0	1	0	1	`{"registers":[1,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":255,"stack":[],"callStack":[],"loopStack":[],"memoryReads":[],"memoryWrites":[]}`	None
CALL	1	4	1	1	`{"registers":[1,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":254,"stack":[],"callStack":[2],"loopStack":[],"memoryReads":[],"memoryWrites":[]}`	None
PRINT	4	5	1	1	`{"registers":[1,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":254,"stack":[],"callStack":[2],"loopStack":[],"memoryReads":[],"memoryWrites":[]}`	1

2. Build and check

Read a number of rounds from 0 through 3. Start task A’s counter at 0 and task B’s at 100. Each round, call A to increment and print its counter, then B to increment and print its counter.

Required instruction types: INPUT, LOOP, CALL, RETURN

Example challenge solution

INPUT
COPY R0 R3
LOAD 0 R1
LOAD 100 R2
LOOP R3
CALL taskA
CALL taskB
RETURN
HALT
taskA: LOAD R1
ADD 1
COPY R0 R1
PRINT
SLEEP 0
RETURN
taskB: LOAD R2
ADD 1
COPY R0 R2
PRINT
SLEEP 0
RETURN

Actual checker fixtures

Case 1

Input: 0
Initial memory: All bytes initially zero
Expected output: None

Case 2

Input: 1
Initial memory: All bytes initially zero
Expected output: 1, 101

Case 3

Input: 3
Initial memory: All bytes initially zero
Expected output: 1, 101, 2, 102, 3, 103

3. Explain the machine

Is CALL/RETURN turn-taking the same as hardware preemption?

Reasoning and teaching note

No. It is a cooperative dispatcher model; actual scheduler policy/quantum belongs to the explicitly labeled systems simulation.

26. Partitioning Work Across Cores

Divide independent jobs and combine their results.

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1. Predict and trace

Before running the Try program, predict its output and trace the first three executed instructions. Track the relevant registers, flags or memory as needed. Then step the program to compare.

STORE 1 0
STORE 2 1
STORE 3 2
STORE 4 3
LOAD [0]
MUL R0
COPY R0 R1
LOAD [2]
MUL R0
ADD R1
PRINT
HALT

Queue input: None

Initialize memory: 0: 1, 1: 2, 2: 3, 3: 4

Try prediction key

Output: 10

Instruction	PC before	PC after	Relevant state	Output
STORE	0	1	`{"registers":[0,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":255,"stack":[],"callStack":[],"loopStack":[],"memoryReads":[],"memoryWrites":[0]}`	None
STORE	1	2	`{"registers":[0,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":255,"stack":[],"callStack":[],"loopStack":[],"memoryReads":[],"memoryWrites":[1]}`	None
STORE	2	3	`{"registers":[0,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":255,"stack":[],"callStack":[],"loopStack":[],"memoryReads":[],"memoryWrites":[2]}`	None

2. Build and check

Four job values are seeded at memory 0–3. Worker even computes value[0]² + value[2]²; worker odd computes value[1]² + value[3]². Call both workers. Print the even total, odd total, and combined total in that order.

Required instruction types: CALL, MUL, LOAD, ADD

Example challenge solution

CALL evenWorker
PRINT
CALL oddWorker
PRINT
LOAD R1
ADD R2
PRINT
HALT
evenWorker: LOAD [0]
MUL R0
COPY R0 R1
LOAD [2]
MUL R0
ADD R1
COPY R0 R1
RETURN
oddWorker: LOAD [1]
MUL R0
COPY R0 R2
LOAD [3]
MUL R0
ADD R2
COPY R0 R2
RETURN

Actual checker fixtures

Case 1

Input: None
Initial memory: 0: 1, 1: 2, 2: 3, 3: 4
Expected output: 10, 20, 30
Required memory reads: 0, 1, 2, 3

Case 2

Input: None
Initial memory: 0: 0, 1: 4, 2: 5, 3: 1
Expected output: 25, 17, 42
Required memory reads: 0, 1, 2, 3

Case 3

Input: None
Initial memory: 0: 10, 1: 1, 2: 2, 3: 3
Expected output: 104, 10, 114
Required memory reads: 0, 1, 2, 3

3. Explain the machine

Does calculating two worker totals sequentially prove parallel execution?

Reasoning and teaching note

No. It verifies decomposition/combination. Independent VM lanes in the systems simulation demonstrate distinct state, not hardware speed claims.

27. Interrupts and Handlers

Handle an event and restore the interrupted foreground value.

Open this lesson →

1. Predict and trace

Before running the Try program, predict its output and trace the first three executed instructions. Track the relevant registers, flags or memory as needed. Then step the program to compare.

STORE 4 240
LOAD 17
CALL handler
PRINT
LOAD [241]
PRINT
HALT
handler: PUSH
LOAD [240]
ADD 1
STORE 241
POP
RETURN

Queue input: None

Initialize memory: All bytes initially zero

Try prediction key

Output: 17, 5

Instruction	PC before	PC after	R0 before	R0 after	Relevant state	Output
STORE	0	1	0	0	`{"registers":[0,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":255,"stack":[],"callStack":[],"loopStack":[],"memoryReads":[],"memoryWrites":[240]}`	None
LOAD	1	2	0	17	`{"registers":[17,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":255,"stack":[],"callStack":[],"loopStack":[],"memoryReads":[],"memoryWrites":[]}`	None
CALL	2	7	17	17	`{"registers":[17,0,0,0,0,0,0,0],"flags":{"zero":false,"negative":false,"overflow":false},"sp":254,"stack":[],"callStack":[3],"loopStack":[],"memoryReads":[],"memoryWrites":[]}`	None

2. Build and check

Read a foreground integer, then an event byte. Store the event at address 240. Call a handler that writes event + 1 to byte memory 241 while preserving foreground R0 with PUSH/POP. Print the restored foreground value, then the stored event result.

Required instruction types: INPUT, PUSH, POP, CALL, STORE

Example challenge solution

INPUT
COPY R0 R1
INPUT
STORE 240
LOAD R1
CALL handler
PRINT
LOAD [241]
PRINT
HALT
handler: PUSH
LOAD [240]
ADD 1
STORE 241
POP
RETURN

Actual checker fixtures

Case 1

Input: 17, 4
Initial memory: All bytes initially zero
Expected output: 17, 5
Expected final memory: 240: 4, 241: 5
Required memory reads: 240, 241

Case 2

Input: -8, 0
Initial memory: All bytes initially zero
Expected output: -8, 1
Expected final memory: 240: 0, 241: 1
Required memory reads: 240, 241

Case 3

Input: 33, 255
Initial memory: All bytes initially zero
Expected output: 33, 0
Expected final memory: 240: 255, 241: 0
Required memory reads: 240, 241

3. Explain the machine

What must a handler restore before foreground resumes?

Reasoning and teaching note

The foreground value/state its caller still needs; event counters may intentionally change. Incrementing 255 gives 256; storing its low byte writes 0.